MPE Forth 7 VFX ARM/Cortex-M Cross Compiler release notes ========================================================= Copyright (c) 2010-2013, 2014, 2015, 2016, 2017, 2018, 2019, 2020, 2021, 2022 MicroProcessor Engineering 133 Hill Lane Southampton SO15 5AF England tel: +44 (0)23 8063 1441 net: mpe@mpeforth.com tech-support@mpeforth.com web: www.mpeforth.com The ARM Cortex compiler can generate code for the original ARM instruction set, for ARMv6M (Cortex-M0/M1) and for the Thumb-2 (Cortex-M3/M4/M7/M33) instruction set. Some support is provided to cope with restrictions in the ARM32 instruction set introduced in the ARMv6A/R (e.g. Raspberry Pi v1) and ARMv7A/R (Cortex-A/R) CPUs. In order to improve maintainability of the code generator, support for ARM CPUs before ARM7TDMI has been removed. In practice, this means that CPUs running in 26 bit mode, without 64 bit multiply, and without the LDRH/STRH instructions are no longer supported. If you still need support for ARM devices before ARM7TDMI, please contact MPE - the ARM7/9/11/XScale compiler is still available. For details of the ARM compiler changes before February 2010, see Release.Arm.txt. v7.61 - 1 November 2022 ===== Enhanced checks for use of R13 or R15 as destination register for M4 and M7 cores. v7.61 - 27 July 2021 ===== Updated SVDparser for 64 bit hosts. v7.61 Build 1629 - 24 September 2020 ================ Rebuild on VFX version 5.11 latest build 297 which includes DocGen. v7.61 Build 1623 - 14 July 2020 ================ Corrected AAPCS interface for 64 bit host. Rebuild on VFX version 5.11 latest build 286. v7.61 Build 1587 - 14 July 2020 ================ Rebuild on VFX version 5.11. Updated for 64 bit host Forths. v7.61 Build 1462 - 8 November 2019 ================ Rebuild on VFX version 5.1. Large number of internal changes and corrections ready for future developments. v7.50 Build 1458 - 31 January 2019 ================ Added Cortex/Tests/TestAAPCS.fth to test the Sockpuppet AAPCS call interface. Fixed the LongLong handling. Changed F.P. constants to start 'F%' rather than '%' in order to avoid name conflicts with binary values. Added FSP@ intrinsic to return R8, the floating point stack pointer, as a new TOS. v7.50 Build 1432 - 2 July 2018 ================ Rewrote local variable code generators for Cortex-M0/M1. v7.50 Build 1378 - 3 March 2018 ================ Added code generators for the 16 bit operations WOR! WAND! WBIC! WXOR! v7.50 Build 1369 - 24 August 2017 ================ Corrected handling of zero-length strings. v7.50 Build 1320 - 29 May 2017 ================ Added FSP! intrinsic to set R8, the floating point stack pointer. The standard Cortex start-up code no longer uses R0. This allows C startup code to pass a parameter to Forth. v7.50 Build 1308 - 19 April 2017 ================ Enhanced Thumb short move generation in assembler and CM3+ code generator. The cross-compiler now checks for imbalance in [IF] ... [THEN] at the end of the file. Please report any failure in MPE files so that we can correct them. v7.50 Build 1273 - 8 November 2016 ================ Corrected stack handling for AAPCS call: void func( void ). Enhanced the AAPCS interface to support Cortex-M0/M1 devices. For Cortex CPUs, the UP! intrinsic no longer touches R0. This allows AAPCS C wrappers to pass a parameter to the Forth start up code. v7.50 Build 1245 - 19 October 2016 ================ Added the SVDconv tool to convert ARM CMSIS SVD files to MPE format Special Function Register files for new processors. To use this tool, read the ARM/Cortex compiler manual and compile the code into the cross compiler *before* executing CROSS-COMPILE. This tool almost totally automates the production of new sfrCPUtype.fth files. v7.50 Build 1245 - 24 August 2016 ================ Added Cortex code generators for the interrupt enable and disable words DI EI DFI EFI This change saves a lot of stack shuffling on both stacks. The instructions are only 16 bits, so in most cases there is a space saving as well as a performance increase. Renumbered some error messages. Removed use of the SWP instruction when +ARM32-Cortex-A/R is active. The SWP instruction is deprecated for ARMv6A/R and ARMv7A/R CPUs. v7.50 Build 1199 - 23 May 2016 ================ Updated the Sockpuppet Forth to C interface to v4 with a more efficient C implementation (thanks, Robert) and a new set of C demo files. Corrected and extended literal handling in the cross compiler and Cortex/VFP32SX.fth. Corrected and optimised externs of the form: int foo( void ); v7.50 Build 1162 - 22 March 2016 ================ The Standard and Professional versions of the compiler now include code generation to call routines in other languages. These routines must conform to the AAPCS standard issued by ARM. See the manual for more details. Words that define calls to routines in other languages are referred to as "externs". The compiler can now handle zero-terminated strings using the Z" notation. v7.40 Build 1162 - 18 January 2016 ================ The code generator leaves R8 alone in all targets: ARM32,CM3/4/7, CM0/1. R8 will be used as the floating point stack pointer in future target releases. Please remove the use of R8 from your CODE and PROC definitions. v7.40 Build 1152 - 18 December 2015 ================ Added more J-Link debugging commands. : reg@ \ reg# -- x Return the data in the saved register (0..15). The CPU must have been halted. : reg! \ x reg# -- Apply the data to the saved register (0..15). : .regs \ -- Display the working registers. : stepOver \ -- If the current instruction is an unconditional BL instruction, step without display until it returns; otherwise perform a single step. There is no display until the end. : from \ addr -- Set the target PC to the given address, e.g. ' from go v7.40 Build 1114 - 28 May 2015 ================ Added VFP instruction set (M4 version) to ARM and Cortex assembler and disassembler. v7.34 Build 1076 - 10 November 2014 ================ Minor changes from the VFX Forth for ARM Linux development. v7.34 Build 1040 - 29 July 2014 ================ Added BLX to ARM disassembler. Corrected EXECUTE and shuffle code generators for Cortex-M0/M1. v7.30 Build 986 - 9 March 2014 =============== Corrected sign-extended fetches W@S and C@S for Cortex-M0/M1. Enhanced some error reporting. Corrected compares for some negative literals with M0/M1 devices. Corrected code generator for NUWWIDEN. Rebuilt on latest VFX and XC7 chassis to fix a problem with escaped strings. v7.30 Build 942 - 1 November 2013 =============== Rebuilt on latest VFX and XC7 chassis. Added support for Segger J-Link for Flash programming and for the Umbilical Forth link. v7.20 Build 840 - 2 September 2013 =============== Rebuilt on latest VFX and XC7 chassis. Corrected some three register operations in the Cortex-M3 assembler. v7.20 Build 836 - 21 September 2012 =============== Rebuilt on latest VFX and XC7 chassis. Added WFE and WFI instrinsics. v7.20 Build 828 - 12 June 2012 =============== Rebuilt on latest VFX. Updated the code generator to take advantage of the escaped string facilities available in the v7.2 cross compiler. See the release notes and the cross compiler manual xc7.pdf for details. v7.10 Build 810 - 6 March 2012 =============== Rebuilt on latest VFX with INI file changes. v7.10 Build 803 - 9 February 2012 =============== Base corrections in assembler tests. Cortex-M4 updates to assembler and disassembler. v7.10 Build 765 - 1 December 2011 =============== Rebuilt on latest XC7 chassis. See Release.xc7.txt for details. Added intrisics (Cortex only) for byte reversal. ByteRevL \ x -- x' ; reorder all four bytes ByteRevW \ x -- x' ; byte swap top and bottom 16 bit pairs ByteRevWS \ x -- x' ; byte swap bottom 16 bits and sign extend ByteRevWZ \ x -- x' ; byte swap bottom 16 bits and zero extend Fixed MVL32+1 macro in assembler and hence also fixed some uses of EXECUTE. v7.10 Build 750 - 27 June 2011 =============== The code generator lays ISB $0F with option $0F rather than the previous $00. According to both ARM v6M and v7M, option $0F is the only one guaranteed by the instruction set. v7.10 Build 617 - 3 May 2011 =============== Use of more short-form Cortex-Mx instructions to improve speed and code density. v7.10 Build 577 - 17 February 2011 =============== Stamp edition: The address of the first CDATA section can be non-zero, for example for STM32 devices. v7.10 Build 548 - 2 November 2010 =============== v7.1 release. See Release.xc7.txt for details. v7.06 Build 0500 - 7 May 2010 ================ Added ARmv5 switches to assembler. ArmArch5 \ -- ; select ARM32 for v5 ArmArch5? \ -- flag ; true if ARM32 for v5 selected Corrected EOR in assembler. v7.06 Build 0463 - 6 April 2010 ================ Corrected Cortex locals entry code for no input paramters. v7.05 Build 0443 - 7 February 2010 ================ Beta release. The Cortex-M3 code generator is functional. The ARM code generator has been retested.