For CPUs that have a cache, the word FLUSHCACHE should be provided, which should write back all modified data and invalidate at least the instruction cache. Newly compiled code was written to data space and the data cache. Invalidating the ICACHE causes the newly compiled code to be executed rather than the previous contents of the instruction cache, which may contain data now modified by the newly compiled code.
For the SA-1110, see the Intel and the ARM Architecture Reference Manual, 2nd edition, ed. David Seal, chapters B2, B3 and B5.
The source code is in the file ARM\CACHESA1110.FTH.
The equate TBASE defines the start address of the MMU tables and must be defined before this file is compiled, and must be on a 64k boundary. Note that this set up performs no memory remapping, and that the adress and size of the DRAM area are set in this file. If you want to use this file with multiple cacheable sections or with other adress assignments, you will have to modify this file.
$C0000000 equ DRAM-START \ start of DRAM
Defines the start address of the DRAM which is to be cached.
4 Mb equ /DRAM \ size of DRAM
Defines the size of the DRAM to be cached.
DRAM-START /DRAM + equ DRAM-END \ end of DRAM + 1
Defines the end address+1 of cacheable DRAM.
variable CE? \ -- addr ; holds true if cache enabled
This variable holds -1 when the cache has been enabled,
or 0 when it is disabled.
code EnableCache \ -- ; Switch on cache & MMU for DRAM
Enable the data cache by constructing a default MMU table
and enabling it. If variable CE? is already set, no action
is taken.
code FlushCache \ -- ; flush DCache and ICache
Flush the ICache and DCache. See the the SA-1110 Developer
Manual section 5.2.3. If the variable CE? is 0, no action
is taken.
code DisableCache \ -- ; Switch off DATA cache & MMU
Disable the data cache.