1987 Rochester Forth Conference Proceedings
on Comparative Computer Architectures

PDFs provided by Paul E. Bennett

Introduction

Lawrence P. Forsley

Invited Papers

Biological Aspects of Neural Nets

Dr. Iben Browning
Abstract

This is a biological talk for computer people.

A Stack-Frame Architecture Language Processor

R. D. Dixon, Wright State University
Abstract

An architecture for a fast 32-bit processor which is designed to support a variety of languages for use in a real-time setting is described. The processor is based on the augmentation of a simple CPU with a set of smart auxiliary memories. These memories allow stack mode and direct access over a fast bus which is not shared with main memory. The possibility of hardware support for context switching in this design makes it a good candidate for demanding imbedded systems such as flight computers.

The Massively Parallel Processor: Architecture and Application

John E. Dorband, NASA/Goddard Space Flight Center
Abstract

Born from ideas conceived during the mid 1970's at NASA's Goddard Space Flight Center, the Massively Parallel Processor) (MPP) was built to explore the application of parallel computing power to satisfy NASA's anticipated vast space and Earth science computing needs, in particular LANDSAT with its extremely large volume of image data. Goodyear Aerospace Corporation began construction of the MPP to government specification in 1979. At that time, no previous attempt had been made at a machine that possessed such a high degree of parallelism. The MPP was delivered to Goddard in May of 1983. In 1984, NASA's Office of Space Science and Applications (OSSA) issued a nationwide request for proposals, seeking scientists interested in pioneering the use of massively parallel processing for scientific computation. A working group of 39 investigators was organized and began their work in October 1985. One year later, most of these investigators presented papers on their work at the First Symposium on the Frontiers of Massively Parallel Scientific Computation held September 24-25, 1986 at Goddard. These papers and a subsequent report written by the working group documented the extremely wide variety of applications that can effectively be processed on the MPP's architecture and permanently established massively parallel processing as a viable and effective manner of satisfying the seemingly overwhelming computational needs of the future.

A 32-Bit Forth Microprocessor

John R. Hayes, Martin E. Fraeman, Robert L. Williams and Thomas Zaremba, Johns Hopkins University
Abstract

We have developed a simple direct execution architecture for a 32 bit Forth microprocessor. The processor has two instruction types: subroutine call and user defined microcode. The processor's data path was designed so that most Forth primitives can be represented with one microcode instruction that executes in a single cycle. The processor uses a single large, uniform address space (2³¹ words) for program, data, and stack storage. The top portions of the parameter and return stacks are cached in the microprocessor to improve performance while retaining a single data path between memory and the CPU. A Forth outer interpreter that supports inline code expansion was written.

Writable Instruction Set, Stack Oriented Computers: The WISC Concept

Philip Koopman, Jr., WISC Technologies, Inc.
Abstract

Conventional computers are optimized for executing programs made up of streams of serial instructions. Conversely, modern programing practices stress the importance of non-sequential control flow and small procedures. The result of this hardware/software mismatch in today's general purpose computers is a costly, suboptimal, self-perpetuating compromise.

The solution to this problem is to change the paradigm for the computing environment. The two central concepts required in this new paradigm are efficient procedure calls and a user-modifiable instruction set. Hardware that is fundamentally based on the concept of modularity will lead to changes in computer languages that will better support efficient software development. Software that is able to customize the hardware to meet critical application-specific processing requirements will be able to attempt more difficult tasks on less expensive hardware.

Writable Instruction Set/Stack Oriented Computers (WISC computers) exploit the synergism between multiple hardware stacks and writable microcode memory to yield improved performance for general purpose computing over conventional processors. Specific strengths of a WISC computer are simple hardware, high throughput, zero-cost procedure calls and a machine language to microcode interface.

WISC Technologies' CPU/32 is a 32-bit commercial processor that implements the WISC philosophy.

Presented Papers

Pride-II Physical Layout Program or Modifying Forth for "Non-Believers"

Tom Almy, Tektronix
Abstract

What does one do to make Forth more palatable to IC and hybrid designers who need the power of a procedural layout language but don't normally program? The interactiveness of Forth helps to get them interested, but the alien environment doesn't help. This paper tells what was done to a standard Forth environment to make it more suitable to these engineers and scientists.

ColorForth: A Powerful Programming Language for the COCO-II

Georges-Emile April, Ecole Polytechnique de Montreal
Abstract

The Radio Shack Color-Computer may be easily modified to accept a Rom-resident version of Forth, especially developped for that machine.

The software has been so arranged as to facilitate the direct transfer of debugged programs into ROM for operation on a stand-alone dedicated board for turn-key operation. Two companion boards were also designed, one being an I/O extender which plugs into the cartridge port of the computer, the other a full featured SBC which shares the same memory and I/O map as the computer ( +I/O extender ). This allows programs to be developped and debugged on the Color Computer, then transferred without modifications to the target board.

Architectures for High-Speed Processing

R. K Bardin, Lockheed Palo Alto Research Center
Abstract

Studies of architectures for high-speed, high-volume signal processing are described on two levels: (1) An experimental system for testing architectures of multi-instruction multi-data processor networks; and (2) an analysis and proposed extension of the Novix NC-4016 architecture. It is proposed that the key design element distinguishing the NC-4016 is not RISC, but simplified instruction decoding, or SID.

Forth and Computer-Assisted Instruction (CAI) I. From Mainframe to Micro: From Coursewriter to Forth

J. Brooks Breeden, Ohio State University
Abstract

Since 1976, the Department of Landscape Architecture at The Ohio State University has used Computer-Assisted Instruction (CAI) in several of its technical course offerings. This informal 35mm slide presentation traces the evolution of the programs from alpha-numeric IBM 370 versions written in IBM's Coursewriter III, through Magnavox Orion-60 plasma panel/35mm rear-slide projector versions written in Phoenix, to IBM PC/Enhanced Graphics versions written in Forth.

Forth and Computer-Assisted Instruction (CAI) II. The Role of Forth in Formative Evaluation of Instructional Materials

J. Brooks Breeden, Ohio State University
Abstract

In 1986, a Computer-Assisted Instruction (CAI) tutorial on superelevation was written in Forth for the Department of Landscape Architecture at The Ohio State University. Later that year, it was used in the research phase of a Ph. D. dissertation: Formative Evaluation Subject Selection: FD/I Cognitive Style. The study investigated learning style as a criterion for selecting students for one-to-one formative evaluation of learning materials.

The original superelevation tutorial was revised based on evaluations by students previously classified as field dependent/independent (FD/I) using the Hidden Figures Test (HFT). A class of 46 junior-level students classified as FD/I were divided into equal groups as control, original tutorial, and revised tutorial. All groups received the same post-test.

The author of the tutorial is highly field-independent, and of students taking the original tutorial, FI's scored significantly higher than FD's. Of students taking the revised tutorial, there was no significant difference between scores of FI's and FD's and both groups scored significantly higher than either group taking the original tutorial. Despite a substantial increase in the amount of material in the revised tutorial, study time remained constant.

This poster session will include a 35mm slide presentation discussing background to the development of the original tutorial and differences between the tutorials resulting from the formative evaluation. The role of Forth, both in the original (PC/FORTH 3.1) and revised (UR/FORTH 1.0) tutorials, will be emphasized.

Organizing and Financing Start-Up Software Venture

Robert E. Brown, Esq., Boylan, Brown, Code, Fowler, Randall and Wilson

Committee Networks: What They Can and Cannot Do

R. J. Brown, Elijah Laboratories, Inc.
Abstract

The committee network is a 2-layer organization of neurons that has special appeal in certain areas of pattern recognition. It has a binary output, is easy to implement, trains quickly, and has fast response due to only 2 layers of cells. The usual activation function for the neurons in a committee network is a simple switching function, making electronic hardware implementations inexpensive and straightforward. The input pattern may be composed of either discrete binary or continuous analog signals.

A High Performance VME Processor Card When 32-Bit Super-Micros Can't Cut It

Phil Burnley and Thomas Harkaway, Xycom
Abstract

Using High Level Languages (HLL) for demanding real time applications is usually not possible on conventional microprocessors. Typically the HLL is only used to program the user interface portion of the application while assembly language is used for the time critical portions. Because the advantages of HLL programming are so great, various approaches to this problem are taken including the use of multiple processors in the same system and using more expensive higher performance processors than the application really requires. This paper discusses an alternate approach; a VMEbus processor which was designed for programming real time applications completely in a HLL.

Advantages of a Fully Segmented Forth Architecture

Jim Callahan
Abstract

The structure of Forth definitions can be exploited to a far greater extent than generally practiced, yielding improved speed, compactness, and flexibility, and virtually eliminating limits on program size. Except for incidental pointers, Forth definitions consist of machine code, definition or parameter lists, and an optional identifier string. The HS/FORTH Development System provided by Harvard Softworks since 1983 compiles words so that each of these portions is segregated into its own segment. Although 8086 family processors form a very natural fit to this organization, it is also appropriate to any processor capable of partial width addressing. This architecture permits programs larger than 64k to be written using fast, compact 16 bit addressing, and is transparent to most applications. Very large programs can utilize additional code and list segments almost as efficiently as the base ones. Each vocabulary also has its own segment, permitting easy dynamic enhancement of both structure and access (ie, reclaiming space from unneeded headers or grafting of hash tables for 10 thousand line/min compilation). Assembled or machine optimized phrases can be very easily included within colon definitions, and colon definitions can be executed from within assembled words. Also, any word can be redefined retroactively at any time, and it is easy to define defining words that create any number of code fields. Finally, the segmented architecture lends itself to the metacompilatlon of separate systems using any threading or segmentation scheme, or easy use of the system as a cross assembler.

An Emulator for Utah Common LISP's Abstract Virtual Register Machine

Harold Carr and Robert R. Kessler, University of Utah
Abstract

A virtual machine emulator (written in Forth) is being used to aid in the development of the Utah Common Lisp compiler. The compiler emits code for an abstract machine with an unlimited number of virtual registers. The register allocator then assigns these virtual registers to real registers and stack frames of the target machine. Once the registers have been assigned, the abstract operations are then mapped to target machine instructions. This paper shows the use of the emulator on virtual register code (before register allocation).

Putting LISP on Forth Base

Harold Carr and Robert R. Kessler, University of Utah
Abstract

There has been much interest in building a Lisp system on top of Forth, especially a Forth engine. A common approach has been to write the Lisp system from scratch, in Forth. We propose an alternate approach based upon the existing Portable Standard Lisp (PSL) system. The PSL compiler emits code for an abstract machine with 15 registers. Typically, the abstract machine code and registers are mapped to target operations and registers/memory locations. In this paper we explore two approaches to bootstrapping Lisp in Forth: 1) create a Forth wordset to emulate the PSL abstract machine, 2) map PSL's abstract machine operations to Forth primitives.

Data Structures for a Forth Environment

Rob Chapman, Idacom Electronics, Ltd.
Abstract

Standard FORTH contains very little in the way of data structures. The only permanent storage structure is a variable. However, due to FORTH's extensibility, it is not limited to variables. A FORTH programmer may create any sort of data structure that may be required, but the FORTH tools for creating these structures are elementary and require a lot of effort to work with complex structures. Most of the time, no formal structure is used and the programmer must remember throughout their program whether they are accessing a word, a byte or even which bits in a bit field. Also if the structure is changed at some point, then all accesses to that structure must be changed as well. As FORTH makes more inroads into large programming environments (particularily 32-bit environments), extensions will be need to make FORTH a more acceptable group programming language. An extension to FORTH is proposed that will provide the programmer with a small but powerful set of tools for the creation and manipulation of data structures. These data type primitives may be used by themselves or combined to create new data type. The programmer can create data types appropriate for their environment and combined them to manipulate complex data structures. This paper is meant as a vehicle for introducing this data structure extension to FORTH and for that reason it will not go into detail about the implementation. Hopefully it will generate interest and lay groundwork for further discussion in this area.

Fuzzy-Forth Rule Based Production System for Real Time Control Systems

L. E. Borges da Silva, G.-E. April and G. Olivier, Ecole Polytechnique de Montreal
Abstract

A fast and efficient FORTH based production system capable of working in a FUZZY environment is described. This production system provides a practical means for structuring knowledge applicable to complex real time control systems. The ordinary meaning of a conditional statement, i.e., a Boolean condition-action pair, was extended in order to cope with the concept of membership function, which allows managing fuzzy variables. A fuzzy variable assumes so called "linguistic values", such as " absolutely large", "small and negative" or even "near zero" instead of numerical values. The fuzzy set approach provides a "natural" means for structuring knowledge applicable to the intelligent solution of engineering problems.

The FUZZY-FORTH production system divides the knowledge in two parts: the "passive rule set" which contains all the available knowledge, and the "active rule set" which contains part of the "passive rule set" and will produce meaningful inferences. The "active rule set" can be up-dated at any time by the rules themselves. This versatility allows the implementation of control systems with several levels of intelligence, which is very useful in systems with real-time learning capability.

The system runs on an in-house version of FORTH, implemented on a Motorola 6809 microprocessor.

Extended Memory Operations for F83

Robert H. Davis
Abstract

A set of extended memory operators based on a 32 bit address or pointer is added to the F83 virtual FORTH machine. This permits accessing all memory in the host microcomputer while still retaining the basic 16 bit model. As an application of using the additional accessable memory, a simple technique for storing FORTH Word definition bodies in extended memory (outside dictionary segment) and dynamically retrieving them is described. When executed, a copy of the definition body is created on an 'execution stack' and execution proceeds as with any other word. For longer definitions or especially for those with significant looping, the runtime retrieval overhead is a relatively minor price to pay to conserve limited dictionary space.

Object-Oriented Local Variables/Data Structures for F83

Robert H. Davis
Abstract

An integrated package of compiler extensions providing symbolic object oriented programming for local variables and data structures is described. The user syntax is simple, consistent, and greatly enhances programming ease and readability of the resultant code. The data structures compiler uses extended memory (32 bit addressing) operations to permit full use of available memory. The approach emphasizes runtime efficiency at the expense of a small increase in compiler complexity.

This paper summarizes the features of the extension package. A paper discussing the details of the approach and implementation has been submitted to the Journal of FORTH Application and Research.

High Performance Neural Networks

W. B. Dress, Martin Marietta, Oak Ridge National Laboratories
Abstract

The anticipated hardware and software needs of the 1990s and beyond will not be met by a continuation of the past evolutionary progress in computing capabilities. At a minimum, a dramatic acceleration over the 60% improvement each year (in processing power, memory capacity, software design, etc.) is needed. Better still, a revolution is called for, and indeed seems to be in the making. Even though the roots of this revolution extend far into the past, the underlying concepts are finding new and forceful expression today.

This revolution has various labels: connectionist models, biologically motivated computing, artificial neural networks, and so on. Some of these paradigms are direct extensions of classical computer science, while others are more radical in approach and extensive in scope. The more conservative approaches retain the preeminent position of the programmer, while the radical ones see eventual extinction of that breed. The conservative approach is extending the paradigms of artificial intelligence--an abstract parody of human behavior, while the radical is creating a synthetic, but nonetheless real, intelligence.

A Forth Implementation of LISP

Tom Hand, Florida Institute of Technology
Abstract

This paper describes a Forth implementation of the language LISP. After discussing various aspects of this implementation, a table of the implemented functions is presented.

BOXER: An Interactive Analysis System for Cardiovascular Physiology Data

Jesse W. Hartley, University of Missouri-Columbia
Abstract

The data gathered during a cardivascular physiology experiment consists of multiple channels of time varying signals, including pressures recorded at various points inside the heart and circulatory system, and blood flow in various arteries supplying the heart. During an experiment, the raw data is recorded on an analog FM magnetic tape recorder. Later, the analog tape is replayed onto a multi-channel chart recorder for detailed analysis. Traditionally, additional derived variables such as derivatives, products, and integrals of various channels would be computed using analog hardware. A typical experiment will require 8 minutes of 5 channels of raw data and the computation of 7 additional derived variables. The bandwidth of each channel is less than 100 Hz. The presentation of the data in graphical form is crucial.

The purpose of this analysis system is to enhance the previous analog instrumentation used for data analysis with a digital system. Initial acquisition of the analog data is done by the program TODISK. The core program, BOXER, displays waveforms and allows the user to select points from those waveforms. This automates counting boxes on chart paper and recording the values. The computation of derived variables is done by the program COMPUTE. These programs have the capability of handling up to 32 channels of data. The programs are written in Fig-Forth and assembly language.

A Unification of Software and Hardware; A New Tool for Human Thought

Glen B. Haydon, WISC Technologies, Inc.
Abstract

The following discussion briefly develops a philosophical basis with which to unify the hardware and software tools of a computer development system. The result is an improved match between software and hardware.

The nature of the human mind and thought processes are not understood. However, there appears to be a mismatch between human thought and the rapidly growing use of computers as tools to help men think. Software engineers and hardware engineers seem to be working in different directions. If we could unify the software and hardware of computers along new lines, we might find a better tool to aid us in our intellectual endeavours. Perhaps a unification of software and hardware would provide a better model to simulate part of the activities of the human brain.

Transportable Forth and Cross Compilers

Rieks Joosten, Pijnenburg Software Developments
Abstract

This article describes the philosophy and experience with prototypes of a Transportable Forth Kernel (TFK). With TFK, the emphasis lies on transportability of the source code without sacrificing facilities such as flexibility and speed. To this end, some vital terminology is developed, nucleus words are stated, and future developments are discussed. TFK prototype systems prove to be not only decent "regular" Forth systems, but also a basis for writing transportable Forth. The latter requires some extra effort from the programmer.

Implementing Forth on the 80386

John E. Lecky, University of Vermont
Abstract

The introduction of a wide range of commercial 32-bit microprocessors by Fairchild, Intel, Motorola, National and others has intensified the drive for native 32-bit Forth implementations. These new processors offer two important advantages as Forth system hosts. First, their 32-bit address spaces provide for the maintenance of enormous Forth dictionaries without resorting to overlaying or segmentation which slow execution and frustrate programmers. Coping with such large dictionaries is increasingly important as Forth is called on to solve more and more complex problems requiring massive programs and data structures.

The second advantage of these new processors is their speed. Forth is often the language of choice for solving real-time control problems. Maintaining execution speed in the face of large control routines and data sets is critical in these applications. The new processors exploit the latest design and fabrication technologies to permit clock rates of up to 30 MHz. At the same time, many instructions execute in fewer clock cycles than were required by earlier processors as more efficient parallel processing is performed internally.

The purpose of this paper is to describe a Forth system that has been developed for one of these processors, the Intel 80386. The 80386, now a key player in the new line of personal computers offered by IBM, will soon enjoy the level of support already enjoyed by some of the earlier entries in the 32-bit market. The 80386 has a "real" mode in which it can execute existing 8086 programs. This feature makes it an attractive system host, as the wide range of existing hardware expansion products already available in the IBM PC-compatible marketplace can be utilized. Similarly, any of the multitude of software products running under MS-DOS or other operating systems can be used as extensions to a Forth-PC system, creating a very powerful and heavily supported workstation or system controller at comparatively low cost.

While the basic architecture of the 80386 closely resembles that of the 8086, a larger instruction set, more orthogonal addressing capabilities, and vastly improved instruction execution times make 80386 Forth an essentially new implementation opportunity. In addition, the hostility of the Intel architecture toward multiple-stack machines makes the job somewhat invigorating.

The 80386-based Forth system described herein has been built around the Intel iSBC 386/20P Single Board Computer running on MULTIBUS 1. The system includes floppy and hard disk support, a full-screen editor, and a complete, standard syntax 80386 assembler. The system also interfaces with a framegrabber and an array processor to allow it to serve as an industrial vision engine. The complete package is targeted for porting to the 386-PC environment as hardware becomes available.

BORON - Yet Another Object Oriented Forth

Steven M Lewis, University of Southern California
Abstract

A system of object oriented extensions to FORTH are described. Objects support inheritance, subclasses, instance variables, both early and late binding and may be intermingled with standard FORTH code. In the absence of specific messages, objects invoke default operations. A uniform means of handling structures of multiple objects is also described. Early binding generates code similar to FORTH code with little run time penalties.

A VLSI Implementation of a Stack-Frame Computer

C. Longway, Ray Siferd and R. D. Dixon, Wright State University
Abstract

The implementation of a 32-bit computer, the SF1 (the architecture is described in the companion paper by Dixon), is described in this paper. A diagram of the implementation, which is pipelined to a depth two, is at the end of this paper, and all names used here come from that diagram or from Dixon's paper.

This work is being done by graduate students and has been separated into distinct functions for each chip. Later versions will require fewer chips. We expect a 125 nanosecond version to be available by spring 1988, and our goal for 1989 is a 20M-instruction/s machine.

Computer-Aided Medical Diagnosis: An Alternative to an "Expert System"

Robert L. Luke, III, M.D.
Abstract

If an expert system is to be of use to a medical practitioner, then the rules as are defined by the expert must apply to the data and the patients of the practitioner. This is unlikely because the data and the patients of the expert are generally subsets of the data and the patients of the practitioner.

This report is of a method in which the intelligence is the frequency of each level of test result in each of the diagnostic categories and the rule is the repeated scaling of the frequency of each diagnosis as each test result indicates a frequency within each diagnostic category for that particular test result. Experience with this method in the classification of proteinuric glomerular disease will be presented. The is relevant to a discussion of the FORTH programming language because this computing application must be complex, fast, flexible and compact.

The Least Common Robot Project

Donald Meyers and A. Richard Miller, Miller Microcomputer Services
Abstract

This paper describes the first stages of a Forth User Group project to develop a Least Common Robot, a simple and affordable design easily interfaced with common microcomputers. Design trade-offs are aimed at providing easy availability of such robots for school and hobby use, for easy programming in standard Forth.

The Fastest File Manager: DATAHANDLER-PLUS

A. Richard Miller and Jill A. Miller, Miller Microcomputer Services
Abstract

DATAHANDLER-PLUS V1.2 is implemented in MMSFORTH and provides fast, compact and easy-to-use abilities for a wide variety of file-manager tasks on personal computers. How compact? It and MMSFORTH reside within 64K of RAM; on an IBM PC, XT, AT, PS2 or compatible computer, DATAHANDLER-PLUS accesses up to the rest of 640K in a very fast data buffer. How fast and easy? A demonstration will be provided. DH+ shares an unusual stand-alone files directory and flexible disk formats with FORTHCOM, FORTHWRITE, DATAHANDLER (its predecessor) and other MMSFORTH application software.

Forth, Esperanto, and the Tower of Babel

A. Richard Miller, Miller Microcomputer Service
Abstract

Esperanto, a logical, efficient and expressive "engineered" language for spoken and written communication, celebrates its 100th anniversary this year. Millions of persons use it worldwide as an international, non-political second language.

Last year at this conference, I described the remarkable similarities between the development of this human language and the Forth computer language, and I extrapolated some messages for Forth's first century of growth. Esperanto activities touch upon Forth in computer-specific ways, as well. This year, I will focus in on issues including Esperanto as a "neutral" conversion language for computerized language translation, international computer exchanges in Esperanto, and the search for a Esperanto-friendly computer language which could be a version of Forth.

High Density Parallel Processing I. The Processor Array and Macro Controller

H. T. Nguyen, R. Raghavan, C. H. Ting and H. S. Truong
Abstract

A GAPP processor array of 11520 processors and its associated controller were built and tested. It allows the processor array to be programmed conveniently using high level languages without sacrificing speed or code efficiency. The system is fully functional. The hardware structure and special features of this system are presented in this report.

High Density Parallel Processing II. Software and Programming

H. T. Nguyen, R. Raghavan, C. H. Ting and H S. Truong
Abstract

Tools, utilities, assemblers and compilers are needed to develop programs which can be run on our parallel processor system, making use of the full power of the GAPP processor array and the Distributed Macro Controller. Some of the software tools are described here and a few examples are also given to illustrated the process of software development on this system.

A Concurrent Architecture for Real-Time Intelligent Process Control

Jack Park and Maj. Stephen R. Le Clair
Abstract

We describe an architecture comprised of three microprocessor-based expert systems, each operating concurrently in a real-time process control environment. This architecture has been applied to the control of an autoclave. Early results are encouraging: successful cure of 256-ply carbon-fiber laminates traditionally requires up to twelve hours of cure time, while the knowledge base created for the concurrent architecture has successfully cured the same laminates repeatably in three hours.

Two of the expert systems are implemented on M68000-based co-processors on an IBM PC-class computer, and the third expert system is implemented in the pc itself. Each expert system is a version of the FORTH-based EXPERT-5, running a qualitative process shell language (QPA), and a knowledge base suited to the process control task. The pc-based expert system serves as a blackboard monitor, controlling communications between the expert systems themselves, and between process sensors, autoclave controls, and the expert systems.

This work is supported by the U.S. Air Force, MLT and FIG laboratories, Wright-Patterson AFB.

A Two-Fisted Algorithm for Moving Data in Tight Places

Walt Pawley, Wump Research & Co.
Abstract

Some years ago, I invented this technique for exchanging the order of two arbitrarily sized, adjacent blocks of data for use in a text editor. I assumed, probably rightly, that the algorithm was well known; until recently, when informal discussions with numerous people knowledgeable about such matters led me to believe that it might not be. Unlike other algorithms that came up in these discussions, this "two-fisted" approach fetches and stores each datum only once. While the overhead required to run the two-fisted algorithm is somewhat more than some others, it can greatly improve speed when the fetching and storing of the data is relatively costly. Applications include such things as text manipulation, heap management or disk de-thrashing. Forth code for the two-fisted block exchange algorithm is included as an appendix.

An OPS5 Expert System Converted to FORPS

James L. Rash, NASA/Goddard Space Flight Center
Abstract

FORPS, a simple Forth-based production system, has been used to reimplement TRAPS, an expert system originally programmed in OPS5 to perform input data checking in Goddard's Communications Link Analysis and Simulation System (CLASS). The FORPS version of TRAPS is implemented both on the CLASS computer and on an IBM PC/AT compatible machine (Hewlett-Packard Vectra). This paper presents results of the TRAPS reimplementation; compares FORPS with OPS5, including efficiency on the HP Vectra; and offers suggestions for enhancements to FORPS.

Forth, Expert Systems, and Mechanical Engineering Education

C. M Sargent, L. G. Watson, R. T. Burton and R. M Westman, University of Saskatchewan
Abstract

As a result of research in the field of Artificial Intelligence, the technology of expert systems has emerged as a popular programming methodology. The use of Forth as a development language for expert systems has been motivated primarily by the need for intelligent real-time control. However, Forth can also be a very powerful tool for expert systems that do not operate in real-time, i.e., consultant systems. We have developed both knowledge-based consultant systems and intelligent real-time monitoring systems using EXPERT-2 and Forth. This paper presents some of the advantages offered by knowledge-based systems in Forth, and describes how these systems have been used as educational tools to train mechanical engineering students.

clusterFORTH: Networking on an OPTO-22 LC2

Adam Shackleford and Jon Waterman, FORTH Inc.
Abstract

A Building Engineer reviews his computer's report of the energy used to heat and cool his building during the last 24 hours. The report shows an unusual increase in energy use in zone seven. Bringing up another report on the screen of his IBM Corp. PC-AT, the Engineer examines the last several hours of operation. For the last three hours, computer twenty three in that zone has been reporting temperatures twenty degrees colder than normal. Its gas burner has been on for those three hours, trying to increase the temperature. The Engineer suspects a failed temperature sensor, but wants confirmation before ordering a repair. Typing the command:

23 BOX PLUG

he's connected to the computer that controls the suspected heating/cooling unit. It will accept commands typed on his PC's keyboard, and display their results on its display. Concurrently, several channels of communication are flowing between his PC and each of 59 similar computers in the same building. That traffic, and his commands travel from his office to the roof-mounted heating/cooling units along a single 4-wire cable. To confirm his suspicion of the temperature sensor, he types a command to read its analog-to-digital converter:

TEMPERATURE READ

The result is displayed on the screen of his PC-AT - the sensor's reading is incorrect. The Engineer calls in the repair order.

The scenario illustrates the capabilities of an application recently developed by FORTH, Inc.. It performs Heating Ventilation and Air Conditioning (HVAC) control for a large multi-building complex. It's written in polyFORTH, our realtime operating system/language. Communications are handled with clusterFORTH network software.

Forth as a Language for Digital Signal Processing

Martin J Tracy, FORTH Inc.
Abstract

The FB320 (Forth board 320), recently developed at FORTH, Inc., supports a digital signal processor (DSP) with the interactive high-level Forth language. The chip used in this first version of the DSP development system is the Texas Instrument TMS32020. It is mounted on a Pacific Microcircuits IBM board, which includes a 50 KHz A/D and D/A converter, up to 128K 16-bit cells of RAM or ROM, and an external bus. The polyFORTH development package runs directly on the TMS32020 chip, using the IBM for terminal and disk support.

Many DSP chips use the Harvard architecture, in which the program and data memory spaces are separated. This allows the DSP chip to use two data buses for rapid evaluation of polynomials. Typically, the program bus is used for coefficients and the data bus for the numeric terms. The TMS32020 is capable of a 16 x 16 signed multiply and shifted 32-bit accumulation in a total of 200 nsec. This architecture required a Forth implementation which combines ROM-ability with separated headers. Furthermore, to coach maximum speed from the Forth, a direct-threaded coding (DTC) implementation was chosen.

Six RePTIL Verbs and the Macintosh

Israel Urieli, Ohio University
Abstract

The Apple Macintosh computer introduced some revolutionary concepts into the personal computer world, one of them being that pointing with a mouse is more intuitive than typing on a keyboard. Significant applications have been developed in which the user need not type on the keyboard at all. Applications are typically developed in terms of an 'event loop', in which the various basic events (such as pressing the mouse button) are continuously polled and resolved.

The token threaded infrastructure of RePTIL is uniquely suited to this environment. The operating system is a self contained kernel and is comprised of the Outer and Inner interpreters (a total of six verbs, 78 bytes of 68000 code) and the Return stack. Thus the input of a keyboard character, and hence the development of the entire RePTIL language can be considered as an application shell on top of this fundamental kernel.

This paper describes the implementation of the RePTIL operating system kernel on the Macintosh computer. An application example of its use is presented in the context of a typical mouse driven application - Conway's Game of Life.

Adding Probabilistic Decision Making to Expert2

L. Glen Watson, University of Saskatchewan
Abstract

In this paper, the author discusses a method of extending EXPERT2 [1], the well known FORTH expert system shell, by incorporating a structure to assign Bayesian probabilities to the hypothesis in the knowledge base and then by using RUNWORDS to manipulate the probabilities after proving any THEN. After the acceptance of a hypothesis, the probabilities of each of the hypothesis being true is listed. The manipulation of the probabilities is carried out as suggested by Charniak and McDermott [2].

Charniak and McDermott, argue that even though the probabilities of occurrence of various symptoms are not independent of each other, useful information can be gained by assuming they are and manipulating the conditional probabilities accordingly. This method of handling the probabilites in EXPERT2 should be of interest. The method used for adding the probability handling to EXPERT2 can also be used for assigning fuzzy confidence numbers [3] to the EXPERT2 decisions.

Abstracts

The Implementation of a Parallel Architecture for the OPS Expert System Language

John D. Allen Jr. and Philip L. Butler, Oak Ridge National Laboratories
Abstract

A parallel processor was designed and built at Oak Ridge National Laboratory for high-speed execution of the OPS expert system language. The parallel architecture is presented along with the first implementation of this architecture.

The first implementation is based on the Motorola MC68000 microprocessor. A custom board was designed that contains four MC68000's each with 512K bytes of memory. There are currently 16 boards in the system for a total of 64 processors. These parallel "rule processors" are controlled by a single Host system, which is a conventional Multibus 68000 computer. This control is through a single Interface Board which allows minimal replication of control and addressing logic.

The OPS language has been implemented in Forth to run on the parallel processor system. The Host system parses the OPS rules and places the left-hand sides of each rule into a rule processor. The rule right-hand sides remain in the Host system for eventual firing. The OPS recognize-act cycle then becomes a cycle between the single Host system and a number of parallel rule processors.

Research sponsored by the U.S. Department of Energy, under contract DE-AC05-840R21400 with Martin Marietta Energy Systems, Incorporated.

Compiling 65816 Forth with a 6502 Metacompiler

Allen Anway, University of Wisconsin-Superior
Abstract

Having a new Apple IIGS and an old Forth metacompiler gave incentive to write Forth in the 65816 native code, a true 16 bit machine. The simple A, memory, X, and Y registers are preserved from the old 6502 into the new 65816 but they can be independently set to 16 bits or 8 bits; or exact 6502 emulation. The conversion stages were:

Write a new Forth assembler, a converted George B Lyons 6502 into a multiple mode assembler. The programmer tells the assembler the mode with words 6502- 816^^ 816^- 816-^ 816--, the normal NEXT exit 816^- being 16 bits M&A, 8 bits X&Y.
Using 6502- code Forth on the IIGS write test examples of code in 816^- native code. Words were written as CODE (DO)' CLC, XCE, 20 .# REP, ... SEC, XCE, NEXT JMP, END-CODE to redefine code into 816^-, run, and put back into 6502- else crash.
Rewrite old meta to new meta, writing I/O references in old 6502- mode.
Compile new 816^- meta kernal relying on metacompiler forcing all interpretation to take place from the old dictionary. Only when the new kernal starts up alone does the machine transfer to the true 65816 native mode.

Do-Loop Exit Address on Return Stack and ?LEAVE

Allen Anway, University of Wisconsin-Superior
Abstract

Since the Forth Do-Loop "wrecks" the return stack with loop indices, I decided in my Forth to put the loop exit address there. My branch implementation uses absolute addresses, so I borrowed >MARK and >RESOLVE to compile an address after (DO) that will later work as an EXIT type of departure. (DO) execution puts the exit, fixed index, and moving index on the return stack in that order.

Advantages: (a) No extra addresses after LEAVE or ?LEAVE are required. This simplifies the branch type compiler as exit addresses are unstructured with respect to IF THEN structure. (b) ?LEAVE now unnests one with -1 flag, zero with 0 flag, but unnests N with N flag. (c) The words (DO) (LOOP) and (+LOOP) set LEAVAL to value 0. The words LEAVE and ?LEAVE set LEAVAL to N. The programmer calls LEAVAL to check if early loop departure took place.

Unnesting N loops is structured: you know the return site. If one seeks a number in a multi-dimensional array, and upon finding it wishes to quit the nested loops, the ( N -- ) ?LEAVE with LEAVAL ( -- N ) trivially solves this otherwise difficult problem.

Toward an Iconic Forth

Greg Dickerhoof, SARNS/3M
Abstract

Iconic languages, also known as visual programming languages, are beginning to appear, not just as academic experiments in computer science, but even as commercial products. Some will fade away, but the best will revolutionize all areas of computer programming -- in productivity, understandability, and in the numbers of people who do programming. Iconic language will become essential to expert systems, simulations, real-time control, database management, as well as general software development, both the quick and the sturdy.

This paper uses examples of innovative software for the Macintosh computer to explore interesting visual paradigms that could be adapted to an iconic programming language.

The author considers it an urgent priority to begin the free development of iconic interfaces built upon, built into, or grafted onto traditional text-based Forths.

The Forth language has much to gain from iconic expression, and it has much to contribute.

LMI Forth for OS/2

Ray Duncan, Laboratory Microsystems Inc.
Abstract

LMI's UR/FORTH interpreter/compiler for the 80x86 and 680x0 is a segmented implementation designed for use under modern multi-tasking operating systems with virtual memory and memory protection. It allows full access to the host's file system, message-passing, and memory allocation services, while achieving high performance via direct threaded code, top-of-stack in register, a native-code optimizer that can be applied selectively to high-level definitions, and use of a completely hashed symbol table rather than the traditional single- or multi-threaded linked dictionary.

At last year's conference, we reported and demonstrated versions of UR/FORTH that ran under 68000 UNIX System V and Microsoft MS-DOS. We have been shipping the MS-DOS version in a complete development package including floating point and graphics support since November, 1986. At this year's conference, we will describe and demonstrate a version of UR/FORTH for the new Microsoft OS/2 operating system. LMI's Forth-83 Metacompiler has also been ported to run on top of UR/FORTH, allowing 80286 and 80386-based computers running OS/2 to be used as development stations for Forth code that will run on a wide variety of microprocessors.

Machine Comprehension as a Control and Planning Tool

Henry Harris, Jet Propulsion Laboratories
Abstract

Conceptual Dependency (CD) theory has been progressively extended from the early theory that represented world knowledge as actions and states to include structures such as goals, planning and scripts. Demonstrations of CD theory have been mainly in the area of language comprehension. A new application of this theory is under development at JPL. This application extends the theory from the recognition and indexing of CD knowledge structures to using these structures to perform man-machine interactions with the goal of spacecraft mission planning and operations. Conceptual Dependency and the implementation of a program to be used as the basis for spacecraft mission planning and operations is discussed.

MATHCALC

Dr. D. Jagerman, AT&T Bell Laboratories
Abstract

This paper presents a number of programs which have been found useful by the author and which have been developed over the past years in response to the needs which have arisen. Some of these needs included the investigation of queueing models with finite buffers, the inversion of generating functions arising from semi-Markov processes - used in the study of error rates for the transmission of data, and in the study of communication protocols - and in the solution of difference equations arising from some models of computer delay. The code for each program is written in the form of individual applications since they were originally so used, however some of them were completely reworked by W. Obi for use as applications and library functions using C and FORTRAN and to be accessed under the UNIX environment; notably, VIED, LAPINV, GEN, CI, and certain of the quadrature programs.

Many of the quadrature programs employ methods which may be considered unusual since they do not depend on the traditional numerical analysis procedures constructed from algebraic polynomials, they are rooted instead in the theory of cardinal series interpolation and quadrature. A basic form is established for quadrature on the entire real line, subsequently, mapping is used as the tool to effect quadrature on subsets.

An introductory discussion of the theory underlying cardinal series quadrature is given before the main discussions of the individual programs. Each program is discussed systematically and at least one example of its use is given. One of the quadrature programs, however, INTO-OO, is based on the Norlund form of the Euler-Maclaurin expansion and utilizes properties of the eigenvalue of the homogeneous Norlund sum. This may be considered to be a departure from the usual mode of applying the Euler-Maclaurin series. Another program containing a variation from the usual is VIED (Volterra integral equation solver) which uses a specially designed quadrature algorithm of greater accuracy than the simple trapezoidal rule but possessing a robustness almost as great. Certain of the traditional procedures are also given - Newton's method for finding zeros, Simpson's rule of quadrature, Runge-Kutta solution of differential equations, and a method of computing the Fourier coefficients of a periodic function. Somewhat unusual is the implementation of Tartaglia's explicit solution of the cubic equation in program CUBIC rather than reliance on iteration procedures.

The programming language which the author uses is PC/FORTH (Laboratory Microsystems Inc.). This language is very convenient for the development of scientific applications; thus, the code for all programs given in this paper are in PC/FORTH which serves as a model for program description. However, in order that these programs be accessible to the UNIX system, a C version of the code is being prepared by the author and will also be given in this paper. Functions which are required in many of the C programs should be written in a separate file to be linked with the main program. For those programs using complex number routines, a separate file is given containing those routines and which is also to be linked to the main program calling them.

The Thunderbird (Mayan Eagle) used as a motif introducing the FORTH code is intended to symbolize the speed and power of FORTH while the Unicorn motif introducing the C code symbolizes the grace and elegance of C.

High-Speed VME-Based Graphics Processor

Jim Jonas and Tom Sargent, Io Inc.
Abstract

We will present a unique architecture for high speed symbol oriented graphics systems with specifics of it's implementation on three graphics engines. This architecture is based upon the principal of copying pre-calculated bit mapped patterns. After the basic pattern set has benn generated, any pattern can be scaled, rotated, color translated, and copied onto the screen at rates up to 9 million pixels per second. Two of the engines are now commercial VME bus products. The higher performance system will be demonstrated running a printed circuit design program. In practice the graphics engine is driven by two 68020 CPU's running Forth software. These share some code in common memory and communicate via bus memory and mail box hardware.

Parallel Processing Using the PC4000-RISC System

George A. Nicol, Silicon Composers
Abstract

A high performance parallel processing system can be configured with multiple PC4000 plug-in processor boards using the PC/XT or AT as the host I/O server. Each PC4000 uses a Novix NC4016 Forth engine as its CPU. A six PC4000 board parallel processing system delivers speeds in the 30 MIPS range.

Coordination of the PC4000 processors is carried out using PCX, a multitasking control and communications system written in Forth and running on the host. PCX supplies each PC4000 processor with keyboard sensing, screen output, disk access, and processor program loading. Using PCX, up to six PC4000s can operate in parallel with each other while running concurrently with the host with minimal host performance degradation. Multiple PC4000 boards can each support a common application or each PC4000 can support an individual applications under PCX.

PCX allows fast convenient switching between the host and PC4000 which speeds up program development turnaround. For example, the PCX host editor allows a programmer to test a section of code without leaving the PCX editor. This is done by switching to the PC4000 directly from the editor, loading and running the new code, then switching back to the editor to make code adjustments.

Applications that can be partitioned easily and that require intensive calculations like the Mandelbrot fractal program are well suited for this kind of parallel processing environment.

Implementation Strategies for Language-Oriented Architectures

L. L. Odette and W. Wilkinson, APEX
Abstract

Each programming language has a corresponding virtual-machine (VM) architecture that can execute a program in that language (a fact language compilers can take advantage of). The instruction sets of these language-oriented architectures are much more often interpreted by software than by hardware.

To the extent that instructions/second is a meaningful measure of hardware power, VM instructions/second is a meaningful measure of interpreter power. Comparisons of performance between VM architectures are colored by the fact that speed depends on both the VM and underlying hardware architectures and the implementation of the interpreter. Nevertheless, comparisions are suggestive. For example, compare the instruction rates in the table below for the VM architectures of a set of A.I. languages.

Language	Encoding Method	Interpreter Implementation Language	Hardware	Clock (MHz.)	VM Instructions Per Second

Smalltalk^[1]	byte code	microcode	Dorado	20.0	300,000
Smalltalk^[2]	byte code	macrocode	68000	12.5	100,000
Prolog^[3]	threaded code	Forth	NC4000	4.0	96,000
Prolog^[3]	threaded code	Forth	NC4000	10.0	320,000 ^est
Prolog^[4]	byte code	C	VAX 11/780	-	66,000
Scheme^[5]	byte code	macrocode	68000	5.0	30,000 ^est

Deutsch, L. P. (1982). The Dorado Smalltalk-80 Implementation: Hardware Architecture's Impact on Software Architecture in Smalltalk-80 Bits of History, Words of Advice. Addison Wesley.
Deutsch, L. P. and Schiffman A. M. (1984). Efficient implementation of the Smalltalk-80 System. In Conference Record of the Eleventh Annual ACM Symposium on Principles of Programming Languages. pp. 297-302
Odette, L. L. and Wilkinson, W.. (1986). Prolog at 20,000 LIPS on the Novix? Proceedings FORML Conference
Gabriel, J., Lindholm, T., Lusk, E L., and R. A. Overbeek (1985). A Tutorial on the Warren Abstract Machine for Computational Logic. Technical Report ANL-84-84 Argonne National Laboratory
Schooler, R. and Stamos, J. W. (1984). Proposal for a Small Scheme Implementation. Technical Report MIT/LCS/TM-267, Massachusetts Institute of Technology

We argue that Forth provides marked advantages over conventional approaches to implementing VM interpreters.

Concept for Forth Engine Based Workstation

Douglas W. Ross, NASA/Goddard Space Flight Center
Abstract

With the introduction of the Novix NC4000 Forth Engine a revolution in work station functionality and use ability is possible. Major advances in hardware system design, and software design, can be achieved with a sophisticated application of this processor, and its imminent successors. This paper looks at various aspects of these issues and presents suggestions as to how these issues can be focused upon and developed for the construction of a Forth engine based workstation.

clusterFORTH in the Factory

J. Waterman and A. Shackleford, FORTH Inc.
Abstract

clusterFORTH is finding an important niche in factory automation. In the last few years, we have developed a standard configuration using IBM PC-AT's or XT's as "masters" in a cluster of Z-80 based single board computers. These communicate using standard RS422 lines with other computers and with a variable number of standard analog and digital modules commonly used in control applications. Up to four IBM's have been configured in a single cluster, each of which supported up to 64 SBC's.

A full polyFORTH system is resident on each of the Z-80 boards. During development, the polyFORTH running on an IBM host provided disk and terminal services to the Z-80 systems. The clusterFORTH capability of "plugging" logically into another computer has made it extremely easy to develop control applications in this configuration.

This paper will describe the cluster environment and the techniques used to develop typical control applications.

Working Group Reports

Esperanto Engine